The present invention relates to a semiconductor memory device, and more particularly to a row redundancy circuit for replacing a defective cell present in a row of a normal memory cell array with a spare cell.
Generally, a semiconductor memory device is provided with a row redundancy circuit to replace a defective memory cell of a normal memory cell array with a spare cell by decoding the row address designating the defective cell. The spare or redundant cell array comprising the spare or redundant memory cells is arranged adjacent to the normal cell array along with decoders for decoding the addresses and selecting the redundant cells.
Each of the minimum array blocks with corresponding sense amplifier groups is usually provided with the respective spare cell array. The number of the minimum array blocks in a single chip tends to be increased as the complexity of the chip increases so as to prevent the operating current drop which is caused by the reduction of the activation of the array. Most of the word line fails are usually caused by so-called cross fail such as bridge between two adjacent word lines. In order to cope with such cross fail, the row redundancy circuit employs a row redundancy set comprising two word lines so as to simultaneously repair the two failing word lines. The two adjacent word lines are defined by least significant bit (LSB) of the row address as the internal signal. The repairing operation is usually accomplished by storing the information of the remaining bits except LSB into the fuse box.
A conventional row redundancy circuit are shown in a block diagram of FIG. 1. The output signals of the row redundant decoders 200 and 200A are respectively connected to the spare word lines SWL1 and SWL2. The signal .phi.X is applied to the row redundant decoders 200 and 200A. The row address signals RA1-RA7 except the LSB RA0 are all transferred to the fuse box 100. The row address signals RA0 and RA0 as LSBs control the row redundant decoders 200 and 200A so as to cut the fuse of the fuse box 100 by using only the information of RA1-RA7 among the row address bits designating the defective memory cell.
Thus, the repairing is possible only when the two adjacent word lines have the same RA1-RA7 and different RA0, so that the repairing probability is only 50%. For example, when there is provided a row redundancy set for each of the minimum array blocks, it is impossible to repair two adjacent word lines pair when a failing occurs between two adjacent word lines pairs divided by LSB. Hence this causes the reduction of the repairing probability to 50% as well as yield of the chips. If there are provided at least two row redundancy sets for each of the minimum array blocks in order to resolve the above problem, the chip areas occupied by the redundant cells and thus the chip size are considerably increased.